An embodiment of the present invention relates to counter control signal generators and refresh circuits including the same.
As demand for mobile apparatuses including mobile telephone terminals, personal digital assistants (PDAs), etc increases, one area of interest is the reduction of the rate of power consumption through dynamic random access memories (DRAMs) employed in such mobile apparatuses. One particular area of interest is reducing refresh currents of mobile-specific DRAMs for lower power consumption thereof.
In contrast to static random access memories (SRAMs) or flash memories among semiconductor memories, DRAMs are characterized by losing data stored in memory cells over time, even while power is being supplied thereto. In order to retain data, DRAMs are basically accompanied with operations for rewriting the data from external systems in a period often called “refresh”. Usually, such a refresh operation is carried out, in retention times that are inherent in memory cells of banks, by activating word lines at least once, or more, and sensing/amplifying data of the memory cells. Retention time is a time for which data can be maintained without a refresh operation after being written into a memory cell.
Several modes of refresh operations are known, e.g., an auto-refresh mode conducted in a normal operation and a self-refresh mode conducted in a power-down mode. The self-refresh operation is controlled by a self-refresh signal generated by a command decoder that receives a command signal. A self-refresh operation is illustrated in FIG. 1.
When a self-refresh signal SELF is activated to a high level in response to an input of a self-refresh command SREF CMD for the self-refresh operation, a self-refresh oscillator generates a pulse of a cyclic signal REF. At every pulse of the cyclic signal, a counter is enabled to sequentially count addresses for accessing memory cells to be refreshed. Thus, sequential steps of the refresh operation progress to the memory cells accessed by the counted addresses.
Here, as shown in FIG. 1, if the cyclic signal REF is generated in an incomplete pulse at a time X corresponding to the terminating the self-refresh operation, the self-refresh operation is inadvertently stopped by a transition of the self-refresh signal SELF to a low level and an address ADD is counted to ‘0000’ from ‘0001’. Subsequently, while the address ADD continues to mechanically change from ‘0001’ to ‘0010’ upon the next generation of the pulse of the cyclic signal REF, if an auto-refresh command AREF is input at a time Y, a refresh fail would be caused due to the incomplete transaction of the prior refresh operation step to the memory cell of the address ‘0001’.